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🔗 Computing 🔗 Computing/Computer hardware

The transputer is a series of pioneering microprocessors from the 1980s, featuring integrated memory and serial communication links, intended for parallel computing. They were designed and produced by Inmos, a semiconductor company based in Bristol, United Kingdom.

For some time in the late 1980s, many considered the transputer to be the next great design for the future of computing. While Inmos and the transputer did not achieve this expectation, the transputer architecture was highly influential in provoking new ideas in computer architecture, several of which have re-emerged in different forms in modern systems.

🔗 Biography 🔗 Computing 🔗 Computing/Computer hardware 🔗 Business 🔗 Women scientists 🔗 Biography/science and academia 🔗 Electrical engineering 🔗 Taiwan 🔗 Women in Business

Lisa Su (Chinese: 蘇姿丰; Pe̍h-ōe-jī: So͘ Chu-hong; born 7 November 1969) is a Taiwanese-born American business executive and electrical engineer, who is the president, chief executive officer and chair of AMD. Early in her career, Su worked at Texas Instruments, IBM, and Freescale Semiconductor in engineering and management positions. She is known for her work developing silicon-on-insulator semiconductor manufacturing technologies and more efficient semiconductor chips during her time as vice president of IBM's Semiconductor Research and Development Center.

Su was appointed president and CEO of AMD in October 2014, after joining the company in 2012 and holding roles such as senior vice president of AMD's global business units and chief operating officer. She currently serves on the boards of Cisco Systems, Global Semiconductor Alliance and the U.S. Semiconductor Industry Association, and is a fellow of the Institute of Electrical and Electronics Engineers (IEEE). Recognized with a number of awards and accolades, she was named Executive of the Year by EE Times in 2014 and one of the World's Greatest Leaders in 2017 by Fortune. She became the first woman to receive the IEEE Robert Noyce Medal in 2021.

🔗 California 🔗 California/San Francisco Bay Area 🔗 Computing 🔗 Computing/Computer hardware

The traitorous eight was a group of eight employees who left Shockley Semiconductor Laboratory in 1957 to found Fairchild Semiconductor. William Shockley had in 1956 recruited a group of young PhD graduates with the goal to develop and produce new semiconductor devices. While Shockley had received a Nobel Prize in Physics and was an experienced researcher and teacher, his management of the group was authoritarian and unpopular. This was accentuated by Shockley's research focus not proving fruitful. After the demand for Shockley to be replaced was rebuffed, the eight left to form their own company.

Shockley described their leaving as a "betrayal". The eight who left Shockley Semiconductor were Julius Blank, Victor Grinich, Jean Hoerni, Eugene Kleiner, Jay Last, Gordon Moore, Robert Noyce, and Sheldon Roberts. In August 1957, they reached an agreement with Sherman Fairchild, and on September 18, 1957, they formed Fairchild Semiconductor. The newly founded Fairchild Semiconductor soon grew into a leader of the semiconductor industry. In 1960, it became an incubator of Silicon Valley and was directly or indirectly involved in the creation of dozens of corporations, including Intel and AMD. These many spin-off companies came to be known as "Fairchildren".

🔗 Computing 🔗 Computing/Computer hardware 🔗 Military history 🔗 Military history/North American military history 🔗 Military history/United States military history 🔗 Military history/Military science, technology, and theory 🔗 Computer Security 🔗 Computer Security/Computing 🔗 Computing/Software 🔗 Military history/Intelligence 🔗 Computing/Computer Security 🔗 Computing/Networking

NOBUS ("nobody but us") are security vulnerabilities which the United States National Security Agency (NSA) believes that only it can exploit. As such, NSA sometimes chooses to leave such vulnerabilities open if NSA finds them, in order to exploit them against NSA's targets. More broadly, it refers to the notion that some signals intelligence capabilities are so powerful or otherwise inaccessible that only the NSA will be able to deploy them, though recent analyses suggest that this advantage may be under stress.

🔗 Computing 🔗 Computing/Computer hardware

The 6800 ("sixty-eight hundred") is an 8-bit microprocessor designed and first manufactured by Motorola in 1974. The MC6800 microprocessor was part of the M6800 Microcomputer System that also included serial and parallel interface ICs, RAM, ROM and other support chips. A significant design feature was that the M6800 family of ICs required only a single five-volt power supply at a time when most other microprocessors required three voltages. The M6800 Microcomputer System was announced in March 1974 and was in full production by the end of that year.

The 6800 has a 16-bit address bus that can directly access 64 KB of memory and an 8-bit bi-directional data bus. It has 72 instructions with seven addressing modes for a total of 197 opcodes. The original MC6800 could have a clock frequency of up to 1 MHz. Later versions had a maximum clock frequency of 2 MHz.

In addition to the ICs, Motorola also provided a complete assembly language development system. The customer could use the software on a remote timeshare computer or on an in-house minicomputer system. The Motorola EXORciser was a desktop computer built with the M6800 ICs that could be used for prototyping and debugging new designs. An expansive documentation package included datasheets on all ICs, two assembly language programming manuals, and a 700-page application manual that showed how to design a point-of-sale terminal (a computerized cash register) around the 6800.

The 6800 was popular in computer peripherals, test equipment applications and point-of-sale terminals. It also found use in arcade games and pinball machines. The MC6802, introduced in 1977, included 128 bytes of RAM and an internal clock oscillator on chip. The MC6801 and MC6805 included RAM, ROM and I/O on a single chip and were popular in automotive applications. The Motorola 6809 was an updated compatible design.

🔗 Computing 🔗 Computing/Computer hardware

The RTX2010 manufactured by Intersil is a radiation hardened stack machine microprocessor which has been used in numerous spacecraft.

🔗 Computing 🔗 Computing/Computer hardware

The Crusoe is a family of x86-compatible microprocessors developed by Transmeta and introduced in 2000. Crusoe was notable for its method of achieving x86 compatibility. Instead of the instruction set architecture being implemented in hardware, or translated by specialized hardware, the Crusoe runs a software abstraction layer, or a virtual machine, known as the Code Morphing Software (CMS). The CMS translates machine code instructions received from programs into native instructions for the microprocessor. In this way, the Crusoe can emulate other instruction set architectures (ISAs).

This is used to allow the microprocessors to emulate the Intel x86 instruction set. In theory, it is possible for the CMS to be modified to emulate other ISAs. Transmeta demonstrated Crusoe executing Java bytecode by translating the bytecodes into instructions in its native instruction set. The addition of an abstraction layer between the x86 instruction stream and the hardware means that the hardware architecture can change without breaking compatibility, just by modifying the CMS. For example, Transmeta Efficeon — a second-generation Transmeta design — has a 256-bit-wide VLIW core versus the 128-bit core of the Crusoe.

Crusoe performs in software some of the functionality traditionally implemented in hardware (e.g. instruction re-ordering), resulting in simpler hardware with fewer transistors. The relative simplicity of the hardware means that Crusoe consumes less power (and therefore generates less heat) than other x86-compatible microprocessors running at the same frequency.

A 700 MHz Crusoe ran x86 programs at the speed of a 500 MHz Pentium III x86 processor, although the Crusoe processor was smaller and cheaper than the corresponding Intel processor.

🔗 Video games 🔗 Computing 🔗 Computing/Computer hardware 🔗 Japan 🔗 Japan/Business and economy 🔗 Video games/Sega

SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.

At the time of introduction, SuperH was notable for having fixed-length 16-bit instructions in spite of its 32-bit architecture. This was a novel approach; at the time, RISC processors always used an instruction size that was the same as the internal data width, typically 32-bits. Using smaller instructions had consequences, the register file was smaller and instructions were generally two-operand format. But for the market the SuperH was aimed at, this was a small price to pay for the improved memory and processor cache efficiency.

Later versions of the design, starting with SH-5, included both 16- and 32-bit instructions, with the 16-bit versions mapping onto the 32-bit version inside the CPU. This allowed the machine code to continue using the shorter instructions to save memory, while not demanding the amount of instruction decoding logic needed if they were completely separate instructions. This concept is now known as a compressed instruction set and is also used by other companies, the most notable example being ARM for its Thumb instruction set.

As of 2015, many of the original patents for the SuperH architecture are expiring and the SH-2 CPU has been reimplemented as open source hardware under the name J2.

🔗 Computing 🔗 Computing/Computer hardware

The Saturn family of 4-bit (datapath) microprocessors was developed by Hewlett-Packard in the 1980s first for the HP-71B handheld computer and then later for various HP calculators (starting with the HP-18C). It succeeded the Nut family of processors used in earlier calculators. The original Saturn chip was first used in the HP-71B hand-held BASIC-programmable computer, introduced in 1984. Later models of the family powered the popular HP 48 series of calculators. The HP48SX and HP48S were the last models to use genuine Saturn processors manufactured by HP. Later calculator models used Saturn processors manufactured by NEC. The HP 49 series initially used the Saturn CPU as well, until the NEC fab could no longer manufacture the processor for technical reasons in 2003. Therefore, starting with the HP 49g+ model in 2003, the calculators switched to a Samsung S3C2410 processor with an ARM920T core (part of the ARMv4T architecture) which ran an emulator of the Saturn hardware in software. In 2000, the HP 39G and HP 40G were the last calculators introduced based on the actual NEC fabricated Saturn hardware. The last calculators based on the Saturn emulator were the HP 39gs, HP 40gs and HP 50g in 2006, as well as the 2007 revision of the hp 48gII. The HP 50g, the last calculator utilizing this emulator, was discontinued in 2015 when Samsung stopped producing the ARM processor on which it was based.

🔗 Computing 🔗 Computing/Computer hardware 🔗 Computing/Software 🔗 Java

Jazelle DBX (direct bytecode execution) is an extension that allows some ARM processors to execute Java bytecode in hardware as a third execution state alongside the existing ARM and Thumb modes. Jazelle functionality was specified in the ARMv5TEJ architecture and the first processor with Jazelle technology was the ARM926EJ-S. Jazelle is denoted by a "J" appended to the CPU name, except for post-v5 cores where it is required (albeit only in trivial form) for architecture conformance.

Jazelle RCT (Runtime Compilation Target) is a different technology based on ThumbEE mode; it supports ahead-of-time (AOT) and just-in-time (JIT) compilation with Java and other execution environments.

The most prominent use of Jazelle DBX is by manufacturers of mobile phones to increase the execution speed of Java ME games and applications. A Jazelle-aware Java virtual machine (JVM) will attempt to run Java bytecode in hardware, while returning to the software for more complicated, or lesser-used bytecode operations. ARM claims that approximately 95% of bytecode in typical program usage ends up being directly processed in the hardware.

The published specifications are very incomplete, being only sufficient for writing operating system code that can support a JVM that uses Jazelle. The declared intent is that only the JVM software needs to (or is allowed to) depend on the hardware interface details. This tight binding facilitates the hardware and JVM evolving together without affecting other software. In effect, this gives ARM Holdings considerable control over which JVMs are able to exploit Jazelle. It also prevents open source JVMs from using Jazelle. These issues do not apply to the ARMv7 ThumbEE environment, the nominal successor to Jazelle DBX.